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### 2.7 SCPU64 emulator features

The XSCPU64 emulator is a simulation of a C64 equipped with a SuperCPU64 V2B. Features:

- 20 MHz asynchronous single cycle 65816 CPU core with proper dummy and invalid cycle handling.
- 128 KiB static RAM, 0-16 MiB SIMM RAM, 64-512 KiB EPROM emulated and their respective timing details.
- All RAM optimization configurations supported with write buffer.
- I/O area access delays, write through to SRAM implemented.
- Memory mappings including cartridge and boot memory map and kernal shadow.
- Hardware registers and switches implemented.
- Replacement SCPU64 ROM compatible with the original to avoid distribution problems
- It’s using the single cycle VICII core for accurate simulation

Still to do:

- Measure and verify VICII interrupt phase shift
- Measure and verify BA phase shift
- SIMM RAM extra 7.5 cycle refresh delay every 10us missing.
- CPU NMI support for “reset” button

The emulation is quite accurate but not perfect. If you code something timing intensive using this simulation please always check it on real hardware to avoid bad surprises.

The hardware itself is asynchronous in nature, therefore caution must be taken to not do long timing loops without synchronization in 20 MHz mode. Also don’t squeeze out the last remaining cycles without leaving a safety buffer. Synchronization points can be created by doing I/O reads or writes and leaving a few hundred cycles left each frame will not hurt.

Otherwise it can happen that the code is running on this version of VICE or my SCPU64 V2+C128D perfectly but nowhere else due to manufacturing variations and frequency drifts.

Next: The keyboard emulation, Previous: CBM-II emulator features, Up: About VICE [Contents][Index]