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The PIA 6520 is a chip with two I/O ports (Parallel Interface Adapter) and four additional handshake lines. The chip is pretty the same for Port A and B, only that Port A implements handshake on read operation and port B on write operation.
Version numbers: Major 1, Minor 0.
Type | Name | Description |
UBYTE | ORA | Output register A |
UBYTE | DDRA | Data Direction Register A |
UBYTE | CTRLA | Control Register A |
UBYTE | ORB | Output register B |
UBYTE | DDRB | Data Direction Register B |
UBYTE | CTRLB | Control Register B |
UBYTE | CABSTATE | Bit 7 = state of CA2, Bit 6 = state of CB2 |